verilog assignment operators

Programmable Logic/Verilog Operators

This page is going to talk about some of the verilog operators.

• 1 Arithmetic Operators
• 2 Logical Operators
• 3.1 Example: Full Adder
• 4 Assignment Operators
• 5 Shift and Rotate
• 6 Concatenation and Replication
• 7 Reduction Operators
• 8 Conditional Operator
• 9 Operator Precedence

Arithmetic Operators [ edit | edit source ]

The arithmetic operators are as follows:

In practice, the division and modulus operators are typically only usable in simulation, not synthesis. Division is a particularly complicated operation, and most programmable chips do not have dedicated divider modules.

Logical Operators [ edit | edit source ]

There are a number of logical operators. Logical operators act on an entire value (multiple bits), and treat the values of "zero" as being "false", and "non-zero" as being "true".

The reduction operators are

• && AND

What happens is that Verilog converts the whole number into either a 1 (if it contains a nonzero bit) or 0 (if it only contains zero), then performs the equivalent bitwise operation. Thus, the answer is also one bit.

!0000 = ~0 = 1 !1101 = ~1 = 0 !1000 = ~1 = 0

!(any nonzero binary number) = ~1 = 0

0000 && 1101 = 0 & 1 = 0 0010 && 1101 = 1 & 1 = 1

0000 || 0110 = 0 | 1 = 1 0000 || 0000 = 0 | 0 = 0

Bitwise Operators [ edit | edit source ]

There are a number of bitwise operators to perform boolean operations on each individual bit in a bus.

Example: Full Adder [ edit | edit source ]

This should help to demonstrate how these bitwise operations are performed.

Assignment Operators [ edit | edit source ]

there are three assignment operators, each of which performs different tasks, and are used with different data types:

The continuous assignment is typically used with wires and other structures that do not have memory. A continuous assignment is happening continuously and in parallel to all other computational tasks. The order of continuous assignments, or their location in the code do not matter.

Non-blocking assignments are assignments that occur once, but which can all happen at the same time. These assignments are typically used with registers and integer data types, and other data types with memory. The following two code snippets with non-blocking assignments are equivalent:

All non-blocking assignments in a single code block occur simultaneously. They happen only once, and the input values for all such assignments are read before the operation takes place (which requires the use of additional latch structures in synthesis).

Blocking assignments are also used with registers and integers (and other memory data types). Blocking assignments occur sequentially, and the code after the assignment will not execute until the assignment has occured.

Shift and Rotate [ edit | edit source ]

if you want to shift right assign shr = a >> 1 // shift a right by 1 bit.

example a=8'b10011011 then x=8'b01001101

assign shr = a >> 2 // shift a right by 2 bits.

example a=8'b10010101 then x=8'b00100101

if you want to shift left assign shl = a << 1 // shift a left by 1 bit.

example a=8'b10011011 then x=8'b00110110

assign shl = a << 2 // shift a left by 2 bits.

example a=8'b10011011 then x=8'b01101100

Concatenation and Replication [ edit | edit source ]

Combines 2 or more than 2 operands

Reduction Operators [ edit | edit source ]

These are the same as the bitwise operations above.

Conditional Operator [ edit | edit source ]

If the Condition is true, the value of <if true> will be taken, otherwise the value of <else> will be taken. Example:

ram[EAB[9:0]] will be assigned to EDB in case ram_rd_en is true.

Operator Precedence [ edit | edit source ]

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System Verilog Operators: A Comprehensive Guide

Niranjana R

December 3, 2023

System Verilog operators : is a hardware description language used in the development and verification of digital circuits and systems. Similar to other programming languages, it has a set of operators that allow designers to perform various operations on the data. System Verilog operators are classified into different categories based on their functionality. Understanding these operators is crucial for designing efficient and error-free digital circuits.

Table of Contents

The basic System Verilog operators include arithmetic, relational, equality, logical, bitwise, and shift operators. These operators are used to perform basic mathematical and logical operations, such as addition, subtraction, multiplication, division, and comparison, and logical operations like AND, OR, and NOT. Advanced System Verilog operators include reduction, concatenation, replication, and streaming operators. These operators are used to perform complex operations on large data sets, such as data compression, encryption, and decompression.

Key Takeaways

• System Verilog operators are used in the development and verification of digital circuits and systems.
• Basic System Verilog operators include arithmetic, relational, equality, logical, bitwise, and shift operators.
• Advanced System Verilog operators include reduction, concatenation, replication, and streaming operators.

Basic System Verilog Operators

In System Verilog, operators are essential building blocks for designing digital circuits. These operators allow us to perform various operations on digital data and manipulate it to achieve the desired output. In this section, we will discuss the three basic types of operators: Arithmetic, Relational, and Logical.

Arithmetic Operators

Arithmetic operators are used to perform mathematical operations on operands. The basic arithmetic operators in System Verilog are:

For example, the expression a = b + c adds the values of b and c and stores the result in a.

Relational Operators

Relational operators are used to compare two operands. The result of a relational operator is either true or false. The relational operators in System Verilog are:

For example, the expression if (a == b) compares the values of a and b and executes the code inside the if statement if they are equal.

Logical Operators

Logical operators are used to perform logical operations on operands. The logical operators in System Verilog are:

For example, the expression if (a && b) checks if both a and b are true and executes the code inside the if statement if they are.

Understanding these basic operators is essential for designing digital circuits in System Verilog. By using these operators, we can perform various operations on digital data and manipulate it to achieve the desired output.

Advanced System Verilog Operators

In addition to the basic operators, System Verilog provides advanced operators to perform complex operations. These operators are an essential part of System Verilog and are widely used in the development of digital circuits. In this section, we will discuss two of the most important advanced operators: Bitwise Operators and Shift Operators.

Bitwise Operators

Bitwise operators are used to manipulate individual bits of a variable. System Verilog provides six bitwise operators: AND, OR, XOR, NAND, NOR, and XNOR. These operators can be used to perform various operations such as masking, setting, and clearing bits.

Shift Operators

Shift operators are used to shift the bits of a variable left or right. System Verilog provides four shift operators: left shift, right shift, arithmetic right shift, and logical right shift. These operators are used to perform various operations such as multiplication and division by powers of two.

In summary, bitwise and shift operators are essential in System Verilog for manipulating individual bits and shifting bits left or right. By using these advanced operators, we can perform complex operations with ease and efficiency.

Assignment Operators in System Verilog

In System Verilog, we use assignment operators to assign values to variables. The most commonly used assignment operator is the “=” operator. We use this operator to assign a value to a variable. For example, if we want to assign the value of 5 to a variable named “a” , we would write “a = 5;” .

System Verilog also provides us with other assignment operators that we can use to perform certain operations on variables while assigning values to them. These operators are listed in the table below:

By using these assignment operators, we can perform operations on variables and assign the result to the same variable in a single statement. This makes our code more concise and easier to read.

Conditional Operators in System Verilog

In System Verilog, conditional operators are used to create conditional expressions. They are a shorthand way to write if/else statements. The conditional operator is also known as the ternary operator because it takes three operands. The syntax of the conditional operator is as follows:

The conditional operator evaluates the condition first. If the condition is true, it evaluates the expression immediately after the question mark. If the condition is false, it evaluates the expression immediately after the colon.

One of the advantages of using the conditional operator is that it makes the code more concise and easier to read. It can also be used in assignments, which can help reduce the number of lines of code.

Another conditional operator in System Verilog is the implication operator. The implication operator is used to create logical implications. It takes two operands and returns a Boolean value. The syntax of the implication operator is as follows:

The implication operator returns true if the condition is false or if both the condition and the expression are true. It returns false if the condition is true and the expression is false.

In summary, System Verilog provides two types of conditional operators: the conditional operator and the implication operator. These operators can help reduce the number of lines of code and make the code more concise and easier to read.

Miscellaneous Operators in System Verilog

In addition to the basic arithmetic, relational, and logical operators, System Verilog provides several miscellaneous operators that can be used in digital circuit design.

Replication Operator

The replication operator {} is used to replicate a single value or a set of values multiple times. The syntax for the replication operator is {N{value}}, where N is the number of times the value is replicated.

For example, {8{1’b0}} represents a vector of eight bits, all set to 0. This operator is useful when designing circuits that require a large number of identical components.

Concatenation Operator

The concatenation operator {} is used to concatenate two or more vectors into a single vector. The syntax for the concatenation operator is {vector1, vector2, …, vectorN}, where vector1 through vectorN are the vectors being concatenated.

For example, {a, b} represents a vector that is the concatenation of vectors a and b. This operator is useful when designing circuits that require combining multiple vectors into a single vector.

Ternary Operator

The ternary operator ?: is a conditional operator that is used to assign a value to a variable based on a condition. The syntax for the ternary operator is condition ? true_value : false_value, where condition is the condition being evaluated, true_value is the value assigned if the condition is true, and false_value is the value assigned if the condition is false.

For example, y = (x>0) ? 1 : 0 assigns the value 1 to y if x is greater than 0, and assigns the value 0 to y if x is less than or equal to 0. This operator is useful when designing circuits that require conditional assignments.

Bit-select and Part-select Operators

The bit-select operator [] and the part-select operator [start:end] are used to select a single bit or a range of bits from a vector, respectively. The syntax for the bit-select operator is vector[index], where vector is the vector being selected from and index is the index of the bit being selected. The syntax for the part-select operator is vector[start:end], where vector is the vector being selected from, start is the index of the starting bit, and end is the index of the ending bit.

For example, a[7:0] represents a vector that consists of the eight least significant bits of vector a. This operator is useful when designing circuits that require selecting specific bits or ranges of bits from a vector.

These operators, along with the basic operators, provide a powerful set of tools for designing digital circuits using System Verilog.

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Verilog operators

The Verilog operators are similar to the C programming language operator that is used to produce results based on the required operation.

Verilog provides different categories of operators

1. Arithmetic operators

The arithmetic operator performs an arithmetic operation on two operands.

2. Logical operators

Logical operators take variables or expressions as operands and it evaluates to 0, 1, or x value.

3. Equality operators

The equality and inequality operator compares two operands bit by bit and results to 1 or 0 if true or false respectively. They will return value as ‘x’ if either operand has x or z bits.

The case equality and case inequality compares two operands bit by bit even for x and z bits and results in 1 or 0 if true or false respectively. They perform an exact bit-by-bit comparison. If any of the bits is not matched, the result will be 0 (false).

• For unequal length in operands, it fills zeroes at MSB, and a comparison is performed.
• The key difference between equality and case equality is in terms of producing results. The case equality never produces an ‘x’ result whereas equality will produce an ‘x’ result if any of the operands has ‘x’ bits.

4. Relational operators

The relational operation is performed on two operands to returns 1 if the expression is true, otherwise returns 0 if the expression is false.

Note: The ‘z’ is treated as ‘x’ in a relational operation.

5. Bitwise operators

The bitwise operator performs bit by bit operation on one operand and a corresponding bit on the other operand. For any mismatch in length, extra zeros are appended. 

• The ‘z’ is treated as ‘x’ in a bitwise operation.
• The bitwise operators (&, |, ~) performs bit-by-bit operation whereas logical operator (&&, ||, ! ) performs a logical operation.

The bitwise operator follows the below truth table in an operation.

Bitwise and operator

Bitwise or operator

Bitwise xor operator

Bitwise xnor operator

negation Operator

6. Conditional operators

Evaluation:

The <conditional_expression> is evaluated first. If the result is

• True, then <true_expression> is evaluated.
• False, then <false_expression> is evaluated.
• X (ambiguous ) then both <true_expression> and <false_expression> are evaluated and their results are compared bit by bit. Each bit position of outcome is returned as  a. bit value if both bits are the same. b.  X if bit value differs.

2:1 MUX or tri-state buffer can be easily implemented by a conditional operator.

2:1 MUX implementation

Tri-state buffer implementation

7. Shift operators

Logical shift: Logical shift operators shift a vector to left or right by a specified number of bits and fill vacant bit positions with zeros.

Arithmetic shift: Arithmetic shift operators shift a vector to left or right by a specified number of bits and fill vacant bit positions with sign bit if an expression is signed, otherwise with zeros.

Note: Shift operators do not wrap around.

8. Reduction operators

The reduction operators give 1-bit output by performing the bitwise operation over a single vector operand.

• Reduction operators work bit by bit from right to left.
• Results of reduction nand, reduction nor and reduction xnor are inverted versions of results of reduction and, reduction or and reduction xor.

9. Concatenation operators

The multiple operands can be appended using a concatenation operator. The operands have to be written in braces and separate themselves with commas.

• Operands can be vector/scalar registers or nets, sized constants, bit-select.
• Unsized operands are not allowed because computed result size is dependent on each operand size.

10. Replication operators

The same number can be replicated for a specific number of times (replication constant) using a replication operator.

• It is recommended to use parentheses in the expressions to avoid ambiguity.
• If parentheses are not used then precedence order is followed as

Arithmetic operator (Highest precedence) -> Relational operator -> equality operator -> reduction operator -> logical operator -> conditional operator (Lowest precedence).

Verilog Tutorials

• The Verilog-AMS Language
• Analog Processes
• Assignment Statements

Assignment Statements 

Contribution .

A contribution statement is used to give values to continuous signals, in particular to branch potentials or flows:

This statement says that the voltage on the branch named ‘res’ should be driven so that the voltage on the branch should equal r multiplied by the current through the branch.

Contributions may be either explicit, as above, or implicit. Implicit contributions have the target on both sides of the contribution operator. For example:

This implements the series combination of a resistor and a capacitor.

Implicit contributions to branch flows can be used to easily create series combinations whereas implicit contributions to branch potentials can be used to create parallel combinations. For example, the following creates the parallel combination of an inductor and a conductor:

Multiple contributions to the same branch in the same analog process accumulate. For example:

This is equivalent to:

Multiple contributions to a branch flow can be viewed as creating multiple parallel branches. For example, the above example is equivalent to the parallel combination of the output of a controlled current source, a conductor, and a capacitor. Similarly, multiple contributions to a branch potential can be viewed as creating multiple series branches.

The target (left side) must be a branch signal: an access function applied to a continuous branch. The branch may be a named (or explicit) branch, or it may be an unnamed (or implicit) branch, which are given as a single net or a pair of nets. When an implicit branch is given as a pair of nets, the branch is assumed to connect the two nets. When an implicit branch is specified as a single net, the branch is assumed to connect that net to ground.

Here is a resistor module that uses a explicitly declared or named branch:

Here is a resistor module that uses a implicitly declared or unnamed branch:

Descriptions that employ unnamed branches are a little more compact, but also the formulation of the branches is constrained (multiple contributions to flows give a shunt toplogy and to potentials gives a series topology). For this reason people use unnamed branches with the branch topology is simple, and switch to named branches for the more complicated topologies.

The actual contributions occur after the analog block has been evaluated, meaning that the branch values do not change between statements in the analog block. As such, so as long as the values of the right-hand side expressions are not affected, the order of the contribution statements is inconsequential. So for example, these two analog blocks are equivalent:

Indirect Assignment 

An indirect assignment is an alternative to the contribution statement. It also drives a particular branch potential or flow so that a given equation is satisfied, but in this case the driven branch potential or flow need not be in the specified equation. This feature is rarely needed, however it occasionally allows you to describe a component that would cumbersome to describe with contributions. For example, it is possible to describe an ideal opamp using:

This can be read as ‘drive V(out) such that V(pin,nin) == 0’.

The left side of the equation must be either a branch potential or flow, the right side is an expression. The equation may be implicit or explicit.

The driven branch must not also be a target of a contribution statement.

Assignment 

A assignment evaluates the expression on its right hand side and then immediately assigns the value to the variable on its left hand side:

The target (left side) of an analog assignment statement may only be a integer or real variable. It may not be signal or a wire.

Contribution versus Assignment 

For people new to Verilog-A and Verilog-AMS, contribution and assignment seem to be doing very similar things, and this can confuse them. Here the differences between contribution and assignment are highlighted.

Verilog Continuous Assignment Statements Tutorial

Continuous assignment statements are an essential aspect of Verilog that allows you to assign values to signals without using procedural blocks. Unlike procedural assignments found in always blocks, continuous assignments are used for modeling combinational logic. In this tutorial, we will explore continuous assignment statements in Verilog and learn how to use them to describe the behavior of combinational circuits efficiently.

Introduction to Continuous Assignment Statements

Continuous assignment statements in Verilog are used to specify the relationship between input and output signals in a combinational circuit. They allow you to assign a value to a signal continuously, meaning the assignment is continuously evaluated as the inputs change. Continuous assignments are used outside procedural blocks and are ideal for describing combinational logic or interconnections between signals.

Example of Continuous Assignment Statements:

Another example:, steps to use continuous assignment statements.

To use continuous assignment statements in Verilog, follow these steps:

• Identify the combinational logic relationship between input and output signals.
• Use the 'assign' keyword to create a continuous assignment statement.
• Specify the output signal on the left-hand side and the combinational logic expression on the right-hand side of the assignment.
• Ensure that the right-hand side expression does not contain any procedural constructs, as continuous assignments are not allowed to contain procedural statements.
• Continuous assignments are evaluated in parallel with no explicit sequencing, making them suitable for combinational logic modeling.

Common Mistakes with Continuous Assignment Statements

• Using procedural statements such as if-else or case statements within continuous assignments.
• Missing the 'assign' keyword before the continuous assignment statement, leading to syntax errors.
• Attempting to use continuous assignments for modeling sequential logic, which is not their intended use.
• Using continuous assignments for outputs in modules with procedural assignments, leading to unexpected behavior.
• Not considering the propagation delays of combinational logic when using continuous assignments, which may affect simulation results.

Frequently Asked Questions (FAQs)

• Q: Can I use continuous assignments inside an always block? A: No, continuous assignments are not allowed inside always blocks. They are used outside procedural blocks to model combinational logic.
• Q: What is the difference between continuous assignments and procedural assignments? A: Continuous assignments are evaluated continuously for combinational logic, while procedural assignments in always blocks are used for modeling sequential logic that executes based on clock edges or event triggers.
• Q: Can I use continuous assignments for bidirectional signals? A: No, continuous assignments can only be used for assigning values to output or wire signals, not bidirectional signals or registers.
• Q: How do continuous assignments affect the simulation time of a Verilog design? A: Continuous assignments add negligible overhead to the simulation time as they represent combinational logic and are evaluated in parallel with no explicit sequencing.
• Q: Can I use continuous assignments for modeling arithmetic operations? A: Yes, continuous assignments can be used to model arithmetic operations in combinational logic. For example, you can use continuous assignments to describe the addition or subtraction of signals.
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?: conditional operator in Verilog

Compact conditional operators.

Many Verilog designs make use of a compact conditional operator:

A comman example, shown below, is an “enable” mask. Suppose there is some internal signal named a . When enabled by en== 1 , the module assigns q = a , otherwise it assigns q = 0 :

The syntax is also permitted in always blocks:

Assigned Tasks

This assignment uses only a testbench simulation, with no module to implement. Open the file src/testbench.v and examine how it is organized. It uses the conditional operator in an always block to assign q = a^b (XOR) when enabled, else q= 0 .

Run make simulate to test the operation. Verify that the console output is correct. Then modify the testbench to use an assign statement instead of an always block . Change the type of q as appropriate for the assign statement.

Turn in your work using git :

Indicate on Canvas that your assignment is done.